1. Field of the Invention
The present invention relates to a digital chrominance signal demodulating device used in a color television set or the like.
2. Description of the Background Art
A chrominance demodulating circuit used in a color television set is for processing a carrier chrominance signal and a color subcarrier to produce color-difference signals. Chrominance demodulating circuits are conventionally formed of analog circuits, but are now often formed of digital circuits with the advent of signal processing technology.
FIG. 11 shows an example of a digital signal demodulating circuit for an NTSC color television signal. An analog composite color television signal received at an input terminal 1 is supplied to an A/D converter 2, where the analog signal is converted into a digital signal, and to a clock/control signal generator 100 for generating clocks and control signals used for digital chrominance signal demodulation. The digital signal output from the A/D converter 2 is input to a horizontal bandpass filter (HBPF) 4 for extracting the frequency components centered on and near the horizontal frequency fsc of the color subcarrier. The signal from the HBPF 4 is supplied, as a carrier chrominance signal, to a chrominance demodulating circuit 5, which outputs color-difference signals via output terminals.
The clock/control signal generator 100 processes the composite color television signal using analog circuits, to generate clock pulses CP1 having a frequency fsc and system clock pulses CP3 having a frequency 4 fsc which are both in phase with the color burst signal. The system clock pulses CP3 are supplied to the A/D converter 2, the HBPF 4 and the chrominance demodulating circuit 5.
FIG. 12A to FIG. 12C show the timing of the chrominance signal demodulation. The digitized composite color television signal from the A/D converter 2 is passed through the HBPF 4 to the chrominance demodulating circuit 5, which also receives the system clock CP3 and the clock pulses CP1. In the case of the NTSC composite color television signal, the frequency fsc of the color subcarrier is fixed at about 3.58 MHz (3.579545 MHz), so that the clock/control signal generator 100 performs the following phase control in order to make the system clock CP3 and the clock pulses CP1 in phase with the color subcarrier.
The composite color television signal input to the clock/control signal generator 100 is supplied to a color burst extractor 101, where a color burst signal is extracted from the composite color television signal. The color burst signal is supplied to a PLL circuit 102, which is also supplied with an output of a frequency fsc from an fsc oscillator 103, and generates clock pulses CP1 (shown in FIG. 12A) of the same frequency and in phase with the color burst signal. The clock pulses CP1 are supplied to a chrominance signal demodulating circuit 5 and to a frequency multiplier 104, which generates clock pulses CP2 (FIG. 12B) of about 4 fsc=14.32 MHz. Because of delays in analog components, the clock pulses CP2 are not necessarily in phase with the color burst signal.
A phase shifter 105 receiving the output of the frequency multiplier 104 phase-shifts the clock pulses CP2 by means of analog circuits to produce a system clock CP3 (FIG. 12C) which is in phase with the color burst signal. The chrominance signal demodulating circuit 5 uses the system clock CP3 as sampling pulses, and extracts color-difference signal data -(B-Y), -(R-Y), (B-Y) and (R-Y) from the digitized carrier chrominance signal shown in FIG. 13A. The solid circles in FIG. 13A to FIG. 13C indicate the samples extracted for (B-Y) signals, and blank circles in FIG. 13A to FIG. 13C indicate the samples extracted for (R-Y) signal. Thus, alternate samples are used for (B-Y) and (R-Y), and color-difference signals (B-Y) and (R-Y) are accurately demodulated as shown in FIG. 13B and FIG. 13C.
In the digital chrominance signal demodulating device described above, a clock/control signal generator 100 is used for generating the system clock CP3 from the clock pulses CP1 in phase with the color burst signal. To produce clocks and control signals used for control over the digital chrominance signal demodulating circuit, the analog frequency multiplier 104 and the analog phase shifter 10S are required, so that the configuration of the entire chrominance signal demodulating device is complicated, and its cost is high.
Moreover, the carrier chrominance signal is A/D-converted at the timing of the system clock CP3, so that even if the clock pulses CP1 output from the PLL circuit 102 is in phase with the color burst signal, the system clock CP3 may not be accurately in phase with the color burst signal. As a result, accurate reproduction of the chrominance signal in the digital signal domain cannot be achieved.